a monolithic 8-bit video a/d converter ad9048 functional block diagram 1 r 2 127 r r/2 r/2 128 r 254 255 r e n c o d i n g l o g i c 13 14 15 16 1 2 3 4 28 23 18 12 27 26 17 19 25 6 10 7 8 9 11 5 l a t c h v cc v ee dgnd agnd d1 (msb) d2 d3 d3 d5 d6 d7 d8 (lsb) nlinv nminv v in r t r m r b convert ad9048 general description the ad9048 is an 8-bit, 35 msps flash converter, made on a high speed bipolar process, which is an alternate source for the tdc1048 unit, and offers enhancements over its predecessor. lower power dissipation makes the ad9048 attractive for a variety of system designs. because of its wide bandwidth, it is an ideal choice for real-time c onversion of video signals. input bandwidth is flat with no missing codes. clocked latching comparators, encoding logic, and output buffer registers operating at minimum rates of 35 msps pre- clude a need for a sample-and-hold (s/h) or track-and-hold (t /h ) in m ost system designs using the ad9048. all digital control inputs and outputs are ttl compa tible. devices operating over two ambient temperature ranges and with two grades of linearity are available. linearities of either 0.5 lsb or 0.75 lsb can be ordered for a commercial range of 0 c to 70 c or extended case temperatures of ?5 c to +125 c. commercial versions are packaged in 28-lead dips; extended temperature versions are available in ceramic dip and ceramic lcc packages. both commercial units and mil-std-883 units are standard products. the ad9048 a/d converter is available in versions compliant with mil-std-883. refer to the analog devices military prod- ucts databook or current ad9048/883b data sheet for detailed specifications. features 35 msps encode rate 16 pf input capacitance 550 mw power dissipation industry-standard pinouts mil-std-883 compliant versions available applications professional video systems special effects generators electro-optics digital radio electronic warfare (ecm, eccm, esm) rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved.
rev. f e2e ad9048especifications (typical with nominal supplies, unless otherwise noted.) electrical characteristics test ad9048jj/jq ad9048kj/kq ad9048se/sq ad9048te/tq parameter (conditions) temp level min typ max min typ max min typ max min typ max unit resolution 8 8 8 8 bits dc accuracy differential nonlinearity 25 ci 0.4 0.75 0.3 0.5 0.4 0.75 0.3 0.5 lsb full vi 1.0 0.75 1.0 0.75 lsb integral nonlinearity 25 ci 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 lsb full vi 1.0 0.75 1.0 0.75 lsb no missing codes full vi guaranteed guaranteed guaranteed guaranteed initial offset error top of reference ladder 25 ci 5 12 512 512 512mv full vi 12 12 12 12 mv bottom of reference ladder 25 ci 4 8 48 48 48 mv full vi 8 8 8 8 mv offset drift coefficient full v 20 20 20 20 v/ c analog input input voltage range full v e2.1; e2.1; e2.1; e2.1; +0.1 +0.1 +0.1 +0.1 v input bias current 7 25 ci 36 60 36 60 36 60 36 60 a full vi 100 100 100 100 a input resistance 25 ci 200 300 200 300 200 300 200 300 k full vi 40 40 40 40 k input capacitance 25 civ 1620 1620 1 620 1620 pf full power bandwidth 8 25 civ 1015 1 015 10 1 5101 5 mhz reference input positive reference voltage 9 full v 0.0 0.0 0.0 0.0 v negative reference voltage 9 full v e2.0 e2.0 e2.0 e2.0 v differential reference voltage full v 2.0 2.0 2.0 2.0 v reference ladder resistance full vi 30 60 125 30 60 125 30 60 125 30 60 125 ladder temperature coefficient full v 0.22 0.22 0.22 0.22 / c reference ladder current full vi 23 40 23 40 23 40 23 40 ma reference input bandwidth 25 cv 10 10 10 10 mhz dynamic performance 10 conversion rate 25 ci 35 38 35 38 35 38 35 38 mhz aperture delay 25 civ 2.4 5 2.4 5 2.4 5 2.4 5 ns aperture uncertainty (jitter) 25 civ 2550 2550 2 550 2550 ps output delay (t pd )25 ci 13 15 9 15 9 15 9 15 ns output hold time (t oh ) 11 25 ci 5 8 58 58 58 ns transient response 12 25 civ 6 20 620 6 20 6 20 ns overvoltage recovery time 13 25 cv 8 8 88ns rise time 25 ci 9 9 9 9 ns fall time 25 ci 14 14 14 14 ns output time skew 14 25 ci 4.5 7 4.5 7 4.5 7 4.5 7 ns nminv and nlinv inputs 0.4 v input current full vi 200 200 200 200 a 2.4 v input current full vi 150 150 150 150 a 5.5 v input current full vi 150 150 150 150 a convert input logic 1 voltage full vi 2.0 2.0 2.0 2.0 v logic 0 voltage full vi 0.8 0.8 0.8 0.8 v logic 1 current full vi 150 150 150 150 a logic 0 current full vi 500 500 500 500 a input capacitance 25 civ 4 6 46 4 646pf convert pulsewidth (low) 25 ci 18 18 18 18 ns convert pulsewidth (high) 25 ci 10 10 10 10 ns absolute maximum ratings 1 v cc to dgnd . . . . . . . . . . . . . . . . . e0.5 v dc to +7.0 v dc agnd to dgnd . . . . . . . . . . . . . . e0.5 v dc to +0.5 v dc v ee to agnd . . . . . . . . . . . . . . . . . +0.5 v dc to e7.0 v dc v in , v rt , or v rb to agnd . . . . . . . . . . . . . . . . . 0.5 v to v ee v rt to v rb . . . . . . . . . . . . . . . . . . . . e2.2 v dc to +2.2 v dc conv, nminv or nlinv to dgnde0.5 v dc to +5.5 v dc applied output voltage to dgnd e0.5 v dc to +5.5 v dc 2 applied output current, externally forced . . . . . . . . . . . . . . . . . . . . . . . . . . . . e1.0 ma to +6.0 ma 3, 4 output short-circuit duration . . . . . . . . . . . . . . . . . 1.0 sec 5 operating temperature range (ambient) ad9048jj/kj/jq/kq . . . . . . . . . . . . . . . . . . . . 0 c to 70 c ad9048se/sq/te/tq . . . . . . . . . . . . . . e55 c to +125 c maximum junction temperature (plastic) . . . . . . . . . 150 c 6 maximum junction temperature (hermetic) . . . . . . . 150 c 6 lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c storage temperature range . . . . . . . . . . . . e65 c to +150 c (v cc = +5.0 v; v ee = e5.2 v; differential re ference voltage = 2.0 v, unless otherwise n oted.)
test ad9048jj/jq ad9048kj/kq ad9048se/sq ad9048te/tq parameter (conditions) temp level min typ max min typ max min typ max min typ max unit ac linearity in-band harmonics dc to 2.438 mhz 15 25 ci 47 50 49 55 47 50 49 55 dbc dc to 9.35 mhz 16 25 cv 48 48 48 48 dbc signal-to-noise ratio (snr) 15 1.248 mhz input frequency 17 25 ci 43.5 44 45 46 43.5 44 45 46 db 2.438 mhz input frequency 17 25 ci 43 44 44 46 43 44 44 46 db 1.248 mhz input frequency 18 25 ci 52.5 53 54 55 52.5 53 54 55 db 2.438 mhz input frequency 18 25 ci 52 53 53 55 52 53 53 55 db signal-to-noise ratio (snr) 16 1.248 mhz input frequency 17 25 ci 43.5 44 45 46 43.5 44 45 46 db 9.35 mhz input frequency 17 25 cv 40.5 40.5 40.5 40.5 db noise power ratio (npr) 19 25 ci v 36.5 39 36.5 39 36.5 39 36.5 39 db differential phase 20 25 ci v1 11 1d egree differential gain 20 25 civ 2 2 2 2 % digital outputs logic 1 voltage full vi 2.4 2.4 2.4 2.4 v logic 0 voltage full vi 0.5 0.5 0.5 0.5 v short circuit current 5 full vi 30 30 30 30 ma power supply positive supply current 25 ci 34 56 34 56 34 56 34 56 ma full vi 58 58 58 58 ma negative supply current 25 ci 90 110 90 110 90 110 90 110 ma full vi 120 120 120 120 ma nominal power dissipation 25 cv 550 550 550 550 mw reference ladder dissipation 25 cv 45 45 45 45 mw notes 1 maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the device may be impaired. functional operation under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 applied voltage must be current-limited to specified range. 3 forcing voltage must be limited to specified range. 4 current is specified as negative when flowing into the device. 5 output high; one pin to ground; 1s duration. 6 typical thermal impedances (no air flow) are as follows: ceramic dip: ja = 49 c/w, jc = 15 c/w; lcc: ja = 69 c/w, jc = 21 c/w; jlcc: ja = 59 c/w; jc = 19 c/w. to calculate junction temperature (t j ), use power dissipation (pd) and thermal impedance: t j = pd ( ja ) + t ambient = pd ( jc ) = + t case . 7 measured with v in = 0 v and convert low (sampling mode). 8 determined by beat frequency testing for no missing codes. 9 v rt v rb under all circumstances. 10 outputs terminated with 40 pf and eight 10 pull-up resistors. 11 interval f rom 50% point of leading edge convert pulse to change in output data. 12 for full-scale step input, 8-bit accuracy attained in specified time. 13 recovers to 8-bit accuracy in specified time after e3 v input overvoltage. 14 output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 15 measured at 20 mhz encode rate with analog input 1 db below full scale. 16 measured at 35 mhz encode rate with analog input 1 db below full scale. 17 rms signal to rms noise. 18 peak signal to rms noise. 19 dc to 8 mhz noise bandwidth with 1.248 mhz slot; four sigma loading; 20 mhz encode. 20 clock frequency = 4 ntsc = 14.32 mhz. measured with 40-ire modulated ramp. specifications subject to change without notice. explanation of test levels test level i e 100% production tested. test level ii e 100% production tested at 25 c and sample tested at specific temperatures. test level iii e sample tested only. test level iv e parameter is guaranteed by design and characterization testing. test level v e parameter is a typical value only. test level vi e all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for military temperature devices; sample tested at temperature extremes for commercial/industrial devices. ad9048 e3e rev. f
ad9048 ? rev. f ordering guide package model linearity temperature option 1 ad9048jj 0.75 lsb 0 c to 70 c j-28a ad9048kj 0.5 lsb 0 c to 70 c j-28a ad9048jq 0.75 lsb 0 c to 70 c d-28 ad9048kq 0.5 lsb 0 c to 70 c d-28 ad9048se/833b 2 0.75 lsb ?5 c to +125 c e-28a ad9048te/833b 2 0.5 lsb ?5 c to +125 c e-28a ad9048sq/833b 2 0.75 lsb ?5 c to +125 c d-28 ad9048tq/833b 2 0.5 lsb ?5 c to +125 c d-28 notes 1 e = leadless ceramic chip carrier; j = j-leaded ceramic; d = cerdip. 2 mil-std-883 and standard military drawing available. pin configurations mechanical information die dimensions . . . . . 140 mils 137 mils 21 mils ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils 4 mils metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ee passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nitride die attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold eutectic bond wire . . . . . . . . . . . . . . . 1 mils gold; gold ball bonding dip (d package) 14 13 12 11 10 9 8 1 2 3 4 7 6 5 17 16 15 20 19 18 28 27 26 25 24 23 22 21 top view (not to scale) ad9048 nc = no connect nminv r m r b agnd nc v in nc nc nc agnd r t convert d8 (lsb) d7 ( msb) d1 d2 d3 d4 dgnd v cc v ee v ee v ee v cc dgnd nlinv d5 d6 lcc (e package) 28 27 1 2 3 426 25 21 22 23 24 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view (not to scale) nc = no connect agnd nc v in nc nc nc agnd dgnd v cc v ee v ee v ee v cc dgnd d4 d3 d2 d1 (msb) nlinv d5 d6 d7 ( lsb) d8 convert r t nminv r m r b ad9048 j-leaded ceramic (j package) 11 510 6789 19 21 20 25 24 22 23 18 17 16 15 14 13 12 top view (not to scale) top view (not to scale) 26 28 27 1 2 3 4 convert d8 (lsb) d7 d6 d5 nlinv r b r m nminv ( msb) d1 d2 d3 d4 agnd nc v in nc nc agnd dgnd v cc v ee v ee v ee v cc dgnd nc = no connect r t nc ad9048 rlow rmid nminv msb d2 d3 d4 rtop conv d8 d7 d6 d5 nlinv dgnd dgnd a gnd ain agnd v cc v ee v cc v cc v cc v ee v ee dgnd figure 1. bonding diagram warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9048 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9048 e5e rev. f pin function descriptions 1k
ad9048 e6e rev. f theory of operation refer to the functional block diagram of the ad9048. the ad9048 comprises three functional sections: a comparator array, encoding logic, and output latches. w ithin the array, the analog input signal to be digitized is co mpared with 255 reference voltages. the outputs of all com- parators whose references are below the input signal level will be high; outputs whose references are above that level will be low. the n-of-255 code that results from this comparison is applied to the encoding logic where it is converted into binary coding. when it is inverted with dc signals applied to the nlinv and/or nminv pins, it becomes twos complement. after encoding, the signal is applied to the output latch circuits where it is held constant between updates controlled by the application of convert pulses. the ad9048 uses strobed latching comparators in which com- parator outputs are either high or low, as dictated by the analog input level. data appearing at the output pins have a pipeline delay of one encode cycle. input signal levels between the references applied to r t (pin 18) and r b (pin 26) will appear at the output as binary numbers between 0 and 255, inclusive. signals outside that range will show up as either full-scale positive or full-scale negative out- puts. no damage will occur to the ad9048 as long as the input is within the voltage range of v ee to 0.5 v. the significantly reduced input capacitance of the ad9048 lowers the drive requirements of the input buffer/amplifier and also induces much smaller phase shift in the analog input signal. applications that depend on controlled phase shift at the con- verter input can benefit from using the ad9048 because of its inherently lower phase shift. the convert, analog input, and digital output circuits are shown in figure 3. 5.0v 13k
ad9048 e7e rev. f layout suggestions designs that use the ad9048 or any other high speed device m ust follow some basic layout rules to ensure optimum performance. the first requirement is to have a large, low impedance ground plane under and around the converter. if the system uses separate analog and digital grounds, both should be solidly connected together, and to the ground plane, as closely to the ad9048 as practical to avoid ground loop currents. ceramic 0.1 f decoupling capacitors should be p laced as closely as possible to the supply pins of the ad9048. for decoupling low frequency signals, use 10 f tantalum capacitors also con- nected as closely as practical to voltage supply pins. within the ad9048, reference currents may vary because of coupling between the clock and input signals. as a result, it is important that the ends of the reference ladder, r t (pin 18) and r b (pin 26), be connected to low impedances (as measured from ground). if the ad9048 is being used in a circuit in which the reference is not varied, a bypass capacitor to ground is strongly recom- mended. in applications that use varying references, they must be driven from a low impedance source. 0.1
ad9048 ? rev. f outline dimensions revision history location page 5/03?ata sheet changed from rev. e to rev. f. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 09/01?ata sheet changed from rev. d to rev. e. change in absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 05/01?ata sheet changed from rev. c to rev. d. change in ordering guide and pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to 28-lead ceramic side-brazed dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 28-lead side-brazed ceramic dual in-line package [sbdip] (d-28) dimensions shown in inches and (millimeters) 28 114 15 0.610 (15.49) 0.580 (12.73) pin 1 0.100 (2.54) max 0.005 (0.13) min seating plane 0.026 (0.66) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.085 (2.16) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) min 1.490 (37.85) max 0.100 (2.54) 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 28-terminal ceramic leadless chip carrier [lcc] (e-28a) dimensions shown in inches and (millimeters) 1 28 5 11 18 bottom view 19 25 26 4 12 0.15 (3.81) ref 0.075 (1.91) ref 0.028 (0.71) 0.022 (0.56) 0.300 (7.62) ref 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) ref 0.020 (0.51) min 0.05 (1.27) 0.095 (2.41) 0.075 (1.90) 0.458 (11.63) 0.442 (11.23) sq 0.458 (11.63) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design c00555??/03(f) 28-lead ceramic chip carrier - j-formed leads [jlcc] (j-28a) dimensions shown in inches and (millimeters) 0.450 (11.43) 0.410 (10.41) 0.022 (0.56) 0.012 (0.30) 0.125 (3.18) max 0.035 (0.89) 0.025 (0.64) pin 1 4 5 26 25 19 18 12 11 top view 0.460 (11.68) 0.440 (11.18) sq sq 0.050 (1.27) 0.310 (7.87) 0.290 (7.37) pin 1 index 0.055 (1.40) 4 5 26 25 19 18 12 11 bottom view 0.040 (1.02) ref x 45 3 places 0.500 (12.70) 0.480 (12.19) 0.020 (0.51) ref x 45 controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
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